In magnetic storage systems, a transducing head writes digital data onto a magnetic storage medium. The digital data serves to modulate the current in the head coil so that a sequence of corresponding magnetic flux transitions are written onto the medium. To read this recorded data, the head passes over the medium and transduces the magnetic transitions into pulses in an analog signal. These pulses are then decoded by the read channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple pulse detector read channel or, as in more recent designs, by using a Partial Response Maximum Likelihood (PRML) read channel. The PRML read channel scheme is preferred over the simpler pulse detection scheme because it decreases the necessary bandwidth. Thus, more data can be stored on the storage medium.
In conventional peak detection schemes, threshold crossing or derivative information implemented in analog circuitry is normally used to detect peaks in the continuous time analog signal generated by the read head. The analog signal is then interpreted at specific bit cell periods. The presence of a peak during the bit cell period is detected as a "1" bit, and the absence of a peak is detected as a "0" bit. Timing recovery adjusts the bit cell periods so that the peaks occur in the center of the bit cells. Errors occur when the bit cells are not correctly aligned with the analog pulse data. Since timing information is derived only when peaks are detected, the input data stream is normally run length limited (RLL) (encoded to limit the number of consecutive "0" bits.)
Intersymbol interference (ISI), due to closely spaced pulses, can cause the peaks to shift from one bit cell to another, resulting in errors when detected. To reduce the effect of ISI, an encoding scheme is employed to ensure that a minimum number of "0" bits occur between "1" bits. For example, a (d,k) run length limited (RLL) code constrains the minimum number of "0" bits between "1" bits to d, and the maximum number of consecutive "0" bits to k. A typical RLL code is a (1,7) 2/3 rate code which encodes 8 bit data words into 12 bit codewords to satisfy the (1,7) constraint. However, the d=1 constraint has the undesirable effect of decreasing the data density due to the decreased bandwidth.
Another technique used to record data, known as Partial Response Maximum Likelihood recording (herein after PRML), increases the data density by compensating for intersymbol interference, thereby obviating the d constraint. Unlike conventional peak detection systems, PRML recording detects digital data by interpreting, at discrete time periods, the actual value of the pulse data. Thus, the analog pulses are sampled at the baud rate and the digital data is detected from these discrete time sample values. This allows for a coding constraint of (0,k) (typically (0,4) 8/9 rate coding) which increases the data density.
The application of Partial Response Maximum Likelihood techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, Sep. 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973. Applying PRML techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recordin", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disk Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991.
Similar to conventional peak detection systems, PRML recording requires timing recovery in order to correctly extract the digital sequence. However, rather than utilizing the continuous analog signal to align peaks to the center of bit cell periods, as in peak detection systems, PRML systems synchronize the sampling of the pulses according to estimated sample values. The sample values can be estimated even in the presence of ISI, and together with the actual signal sample values, used to synchronize the sampling of the analog pulses in a decision-directed feedback system.
Normally, a phase-locked loop (PLL) circuit controls the timing recovery in PRML recording. A phase detector processes the signal samples to generate a phase error between the actual and desired frequency. This phase error operates to adjust the sampling frequency which is typically the output of a variable frequency oscillator (VFO) with the phase error as the control input. The output of the VFO controls the sampling period of an analog-to-digital (A/D) converter. It is necessary to first lock the PLL to a reference or nominal sampling frequency so that the desired sampling frequency, with respect to the analog pulses representing the digital data, can be acquired and tracked.
One technique for locking the PLL to a reference frequency is disclosed in U.S. patent application Ser. No. 07/954,350, which is assigned to the same entity as this application. This technique, as shown in FIG. 2A, injects into the A/D converter a sinsusoidal signal at one fourth the nominal sampling frequency. A frequency error, computed from three sample values (.function.e=-Sgn(Y.sub.N -1)*(Y.sub.n +Y.sub.n -2)), controls the VFO to lock its frequency to the nominal sampling frequency. As shown in FIG. 2B, if the sampling frequency is too fast, the frequency error control signal .function.e is negative and the frequency decreases. If the sampling frequency is too slow, .function.e is positive, as shown in FIG. 2C, and the frequency increases.
The problem with this technique is that the PLL will not lock to the correct reference frequency if there is a DC offset in the sinusoidal signal. Further, the sensitivity is low because only half of a period of the sinusoidal signal is used to compute the frequency error. As a result, this technique is susceptible to errors due to noise in the channel and quantization.
There are also prior art techniques for acquiring and tracking the sampling frequency. These schemes are based on a timing gradient computed from the actual signal samples and estimated signal samples obtained from symbol-by-symbol decisions. See "Timing Recovery in Digital Synchronous Receivers" by K. H. Mueller and M. Mueller, IEEE Transactions on Communications, Vol.Com-24 (1976) , pp. 516-531. However, the prior art techniques have drawbacks which are overcome by the present invention. One inherent drawback is that during acquisition the sampling point may occur at the point halfway between the desired sampling times. Consequently, the method for correcting the phase may reverse its direction of adjustment several times in the vicinity of this unstable equilibrium point for an extended period of time. Although this "hang-up" effect does not frequently occur, the length of the acquisition preamble must be sufficiently long so that the system may still synchronize in this situation. A long preamble reduces the total amount of storage space available for user data.
A method for avoiding the "hang-up" effect in order to reduce the preamble length is disclosed in U.S. Pat. No. 4,890,299, an overview of which is provided in FIG. 3. With this method, a sliding threshold, based on past estimated values .about.X(n), introduces a hysteresis effect that makes reversals in timing phase adjustments very unlikely. However, the estimated sample values .about.X(n) are reconstructed from the signal sample values Y(n) and are therefore subject to error. Errors in the estimated sample values increase again the necessary length of the acquisition preamble.
A further problem not resolved by the prior art is the non-linear characteristic of the timing gradient circuit when tracking arbitrary user data. Because the method for calculating the timing gradient is based on approximating the slope of the pulses, the gain of the timing gradient circuit varies when tracking arbitrary user data due to inconsistent pulse slopes. This variation in gain results in less than optimum timing recovery.
Thus, it is a general object of the present invention to improve the timing recovery method in synchronous partial response magnetic recording systems. A more specific object is to lock the timing recovery loop to a nominal sampling frequency by a technique not affected by a DC offset in the analog signal. A further object is to increase the sensitivity of the lock to reference process in order to decrease susceptibility to errors caused by noise. Yet another object is to acquire the sampling frequency more efficiently by avoiding errors in reconstructing the estimated sample values, thereby reducing the necessary length of the acquisition preamble. A final object is to reduce the gain variations in the timing gradient computation when tracking arbitrary user data.